Astera Labs
Technology
JuniorDesignVerificationEngineer
Neural analysis suggests this role is
optimal for Entry candidates.
“Junior Design Verification Engineer at Astera Labs. Skills: Design Verification, ASIC verification, SystemVerilog, UVM. Develop ASIC verification environments. Develop SystemVerilog/UVM components”
What You'll Achieve.
Ensure silicon performs flawlessly; Meet rigorous demands
Industry & Context.
Analytical skills; Debugging techniques; Solving technical puzzles
What They're Looking For.
Must Have
Bachelor's or Master's degree, Digital Logic understanding, C/C++ or Python programming, Verilog or SystemVerilog familiarity, Curiosity for finding bugs, Attention to detail, Fluent in Hebrew, Fluent in English
Nice to Have
Master's degree, Python or Tcl scripting proficiency, UVM/OVM exposure, Constrained-random verification exposure, PCIe, Ethernet, or DDR understanding
What You'll Do.
Develop ASIC verification environments
Develop SystemVerilog/UVM components
Maintain SystemVerilog/UVM components
Execute verification plans
Implement functional coverage models
Analyze coverage results
Improve verification methodology
Identify hardware bugs
Root-cause hardware bugs
Resolve hardware bugs
Solve verification challenges
How You'll Work.
Team & Collaboration
Design engineers; Fast-paced R&D environment; Team-oriented R&D environment
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity. Key Responsibilities Verification Environme
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