Micron Technology
Semiconductor
IODesignArchitect–HighSpeedMemoryInterfaces(m/f/d)
Neural analysis suggests this role is
optimal for Senior candidates.
“IO Design Architect – High Speed Memory Interfaces (m/f/d) at Micron Technology. Skills: IO Design Architecture, High-speed memory interfaces, Mixed-signal IO. Define IO and PHY concepts. Perform block-level simulation”
Industry & Context.
Feasibility checks; Block-level analysis
What They're Looking For.
Must Have
10 years designing mixed-signal IO blocks, Schematic design and simulation, Proficiency with SPICE, Cadence or Synopsys schematic entry, Understand, model, evaluate block-level behavior, Experience in Unix/Linux environments
Nice to Have
Scripting skills for analysis or automation, Familiarity with extraction and modeling tools, Collaborating with cross-functional teams
What You'll Do.
Define IO and PHY concepts
Perform block-level simulation
Perform feasibility checks
Review schematic-level implementation
Guide schematic-level implementation
Support verification activities
Support silicon bring-up
Support debug activities
How You'll Work.
Team & Collaboration
Global cross-functional teams; Design teams
Full Job Description
**Our vision is to transform how the world uses information to enrich life for** _**all**_**.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Department Overview** Our Munich engineering team develops mixed‑signal and IO solutions for next‑generation memory technologies. The group partners closely with global analog, digital, and product teams throughout the design and silicon lifecycle. **Role Overview** We are hiring an IO Design Architect to design new architecture, analysis, and validation of high‑speed memory IO. This role combines hands‑on circuit understanding with system‑level thinking and close collaboration across multiple design teams. **Responsibilities** * Define and own the IO and PHY concepts for high‑speed memory interfaces * Perform block‑level simulation, analysis, and feasibility checks * Review and guide schematic‑level implementation to align with architectural intent * Support verification, silicon bring‑up, and debug activities * Collaborate with global cross‑functional teams to ensure accurate system integration * Use automation and AI‑based tools to improve modeling and analysis workflows **Required Qualifications** * Minimum 10 years of experience designing mixed‑signal IO blocks, including **schematic design and simulation** * Proficiency with **SPICE** or similar circuit simulation tools * Hands‑on experience with **Cadence or Synopsys schematic entry environments** * Ability to understand, model, and evaluate block‑level behavior * Experience working in Unix/Linux environments **Preferred Qualifications** * Scripting skills (Python, TCL, SKILL, Perl or similar) for analysis or automation * Familiarity with extraction and modeling tools * Experience collaborating with cross‑functional design teams in a semiconductor environment The base salary range that Micron esti
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