HSIOFunctionalandPowerManagementEngineer

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to be part of the HW ArchDev team. The SSG team is uniquely positioned to have an end-to-end view of the product development cycle - from early arch definition, through bringup, to product release. Our ArchDev arm is a hub for all silicon and system-level feature development, cost-benefit analysis, system integration solutions, and system POR alignment. As a member of this team, you will dive into next-gen high-speed interconnects like NVLink and NVLink-C2C to make advancements in efficiency and stability. This position offers the opportunity to have a real impact in a dynamic, technology-focused company, impacting product lines ranging from artificial intelligence to consumer graphics to self-driving cars and more. **What you’ll be doing:** * Contribute to the design of the next generation of high-speed IOs, including NVLink and NVLink-C2C. * Responsible for IO power optimizations and continuing to push energy efficiency. * Ensure interoperability with connected devices and system components in complex interconnect topologies * Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams * Work closely and proactively with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations, and AE teams to drive design, development, debug, and release of next-generation products. **What we need to see:** * BS or MS degree in EE/CE or equivalent experience * Minimum 10 years working on HSIO with the following capacity - power management, use case analysis, perf/power modeling, bringup, and/or debug. * Ownership and working experience in some of the following areas: * Experience with system-level and interconnect power management optimizations * Silicon and platform-level power modeling for active/idle use cases * Understanding of firmware/driver structures and their interaction with HW. * Track record of influence,