Micron Technology
Technology
High‑SpeedRTLDesignEngineer
Neural analysis suggests this role is
optimal for Mid+ candidates.
“High‑Speed RTL Design Engineer at Micron Technology. Skills: RTL Design, Timing Closure, Digital Logic. Design timing-critical RTL blocks. Implement timing-critical RTL blocks”
Industry & Context.
Debugging; Troubleshooting; Root cause analysis
What They're Looking For.
Must Have
SystemVerilog / Verilog RTL proficiency, FSM design and implementation, Reset synchronization, Clock-domain crossing concepts, Timing-critical control logic understanding, Setup/hold timing fundamentals, Critical-path sensitivity, Multi-mode and settings-based behavior, Mixed-signal interaction exposure, RTL lint and CDC checks familiarity, Synthesis and basic STA reports familiarity, DFT-friendly RTL practices familiarity, UPF and LEC familiarity, RTL sign-off debug ability
Nice to Have
PMICs experience, Mixed-signal SoCs experience, Companion ICs experience, Industry-standard specifications exposure, Basic scripting skills (Python / Tcl), RTL–DV–PD handshakes experience
What You'll Do.
Design timing-critical RTL blocks
Implement timing-critical RTL blocks
Develop RTL with attention to latency
Develop RTL with attention to deterministic behavior
Develop RTL with attention to race-free logic
Develop RTL with attention to metastability avoidance
Write nanometer-process-aware RTL
Ensure RTL is clean for synthesis
Ensure RTL is clean for static timing analysis
Ensure RTL is clean for ECO cycles
Implement clock-domain crossings (CDC)
Review clock-domain crossings (CDC)
Design reset and initialization logic
Support power-aware behavior
Support mode-dependent behavior
Resolve port-list mismatches
Resolve clock dependencies
Resolve reset dependencies
Resolve mode interaction issues
Debug integration issues
Clarify design intent
Address timing issues
Simplify control paths
Add limited pipelining
Participate in RTL reviews
Participate in design reviews
Maintain clear documentation
How You'll Work.
Team & Collaboration
Verification engineers; Senior engineers
Communication Scope
Documentation
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **Key Responsibilities** **High** ‑**Speed RTL Design & Implementation** * Design and implement **timing** ‑**critical RTL blocks**, including: * Control and sequencing FSMs * Power‑up, shutdown, and mode‑transition logic * Register banks and configuration logic * Telemetry and monitoring datapath * Develop RTL with attention to **latency, deterministic behavior, race**‑**free logic, and metastability avoidance**. **Nanometer** ‑**Process** ‑**Aware RTL Coding** * Write RTL that is robust to: * Tight setup and hold margins * Clock skew and uncertainty * Multi‑cycle and false‑path constraints * Process, voltage, and temperature (PVT) variation * Ensure RTL is **clean for synthesis, static timing analysis, and ECO cycles** in sophisticated technology nodes. **Clocking, Reset & Power**‑**Aware Logic** * Implement and review **clock** ‑**domain crossings (CDC)** using proven synchronization techniques. * Design **reset and initialization logic** to ensure predictable system startup and recovery. * Support **power** ‑**aware and mode**‑**dependent behavior** as the need arises by system operation. **Integration & Debug** * Integrate RTL blocks into larger subsystems or top‑level designs, resolving: * Port‑list mismatches * Clock and reset dependencies * Mode interaction issues * Debug RTL and integration issues using simulation waveforms and tool feedback. **Verification & Timing Closure Support** * Work closely with verification engineers to: * Clarify design intent and corner cases * Fix RTL issues uncovered during verification * Address timing issues identified during synthesis or place‑and‑route by **refining logic, simplifying control paths, or adding limited pip
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