Graphcore
Artificial Intelligence computing systems
HardwareValidationandDebugEngineer-DDR
Neural analysis suggests this role is
optimal for Mid+ candidates.
“Hardware Validation and Debug Engineer - DDR at Graphcore. Skills: Hardware Validation, Debug, DDR, LPDDR5, Signal Integrity, Root-cause analysis. Perform Validation and Debug for new hardware platforms. Debug PCB, power, signal integrity, and interface issues”
What You'll Achieve.
Help create and execute the bring-up and debug of our cutting-edge system platforms; Show that they will operate correctly over all conditions in the final product
Industry & Context.
Debug PCB, power, signal integrity, and interface issues; Validate and debug high-speed memory interfaces and slow speed interfaces; Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation; Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour; Identify root causes and drive corrective actions across hardware and firmware domains; Root-cause analysis; Subsystem debug
What They're Looking For.
Must Have
Hardware Debug, LPDDR validation and tuning, Signal integrity analysis, DDR training and margin analysis, Protocol-level debugging, Root-cause analysis, Low-level system integration, An ability to work independently without daily oversight, Independently performs board bring-up and subsystem debug, Drives issue resolution across teams, Use advanced lab instrumentation including: High-bandwidth oscilloscopes BERT systems VNA/TDR equipment, Hands-on experience with: LPDDR5 memory subsystems, Hands-on experience with: LPDDR5 compliance testing
Nice to Have
Knowledge of PCBA and system level technologies, Ethernet validation, PCIe, Background knowledge of ATE systems and capabilities, The ability to code or script automation and data analysis using appropriate coding languages such as Python, LabView and BASH
What You'll Do.
Perform Validation and Debug for new hardware platforms
Validate and debug high-speed memory interfaces and slow speed interfaces
Support LPDDR5-9600 initialization
and stability validation
Analyse DDR timing margins
and training behaviour
Identify root causes and drive corrective actions across hardware and firmware domains
Create bring-up documentation
Concentrate on mainly manual testing of systems in the lab with the aid of some automation
How You'll Work.
Team & Collaboration
Work with Architecture, Silicon Engineering, Hardware Engineering and the Firmware team; Drives issue resolution across teams; Working closely with: PCB design engineers Power engineers Signal integrity engineers Embedded software teams
Full Job Description
Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are expending our labs in Bristol which will play a central role in Graphcore's work building the future of AI computing. We are looking for a Validation and Debug engineer to work with Architecture, Silicon Engineering, Hardware Engineering and the Firmware team to help create and execute the bring-up and debug of our cutting-edge system platforms. As such you will need to develop a detailed understanding of our silicon and platform products. Your role will be to create and execute Validation and Debug plans of our silicon devices and platforms in systems to show that they will operate correctly over all conditions in the final product. This Validation will also involve debugging of hardware and firmware. You will concentrate on mainly manual testing of systems in the lab with the aid of some automation. Responsibilities and Duties Perform Validation and Debug for new hardware platforms. Debug PCB, power, signal integrity, and interface issues. Validate and debug high-speed memory interfaces and slow speed interfaces LPDDR5-9600 memory interfaces SPI/I2C/I3C/UART Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation. Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour. Identify root causes and drive corrective actions across hardware and firmware domains. Create bring-up documentation, test procedures, and debug reports. Working closely with: PCB design engineers Power engineers Signal integrity engineers Embedded software
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