FPGAVerificationEngineer-UVMArchitect

Immediately Hiring with a $5000 sign on bonus! Build the verification systems behind mission-critical FPGA designs as a Senior FPGA Verification Engineer (UVM / SystemVerilog / DO-254). Open to Senior-Level Engineers stepping into Architect roles Quest Defense Systems & Solutions (QDSS) is hiring a Senior FPGA Verification Engineer to lead the design and build of UVM-based verification environments for complex, safety-critical systems. In this role, you’ll own how verification is done—from testbench architecture to coverage closure—while helping teams deliver reliable FPGA designs used in real-world aerospace applications. This is a hands-on technical leadership role. You’ll still be close to the code, but also guide strategy, mentor engineers, and improve how verification is executed across programs. Location: Remote (U. S. based) Travel: Occasional Clearance: U. S. Citizen or Permanent Resident required What You’ll Do Lead development of SystemVerilog / UVM verification environments for FPGA designs Build and improve testbenches, agents, scoreboards, monitors, and sequences Define verification strategy, test plans, and coverage goals Drive functional, code, and assertion coverage closure Support both simulation and emulation workflows (Veloce or similar) Review and improve existing verification environments and processes Guide engineers on UVM best practices and debug complex issues Support DO-254 verification activities (requirements traceability, test evidence, audits) Work closely with design, systems, and program teams What You Bring 8–12+ years of experience in FPGA or ASIC verification Strong hands-on experience with SystemVerilog and UVM Experience building UVM testbenches and reusable verification environments Background in simulation, debugging, and coverage-driven verification Experience with tools like QuestaSim, VCS, or similar Understanding of hardware interfaces and RTL design Ability to lead technical efforts and guide other engineers Experience bui