One Thing
Semiconductor
FECPIEPIMTS
Neural analysis suggests this role is
optimal for Senior candidates.
“FE CPIE PI MTS at One Thing. Skills: Process integration, Yield improvement, Semiconductor fabrication. Develop best optimum process. Achieve product maturity”
What You'll Achieve.
Deliver leading edge process capability; Deliver best-in-class bits per wafer; Deliver highest quality; Deliver fastest speed; Achieve product maturity
Industry & Context.
Logical thinking; Model based problem solving; Data driven decision making; Root cause analysis
Travel to Micron sites as necessary, Travel to Micron sites as vital
What They're Looking For.
Must Have
7+ years of experience in process related role, Bachelors/Masters/PhD. in EE, Materials Engineering, Materials Science, Physics and Chemical, Good logical thinking, Knowledge in Semiconductor Fabrication process flows, Understanding of DRAM and NAND operation and structure, Good model based problem solving, Data driven decision making, Presentation skills, Proven track record to fix and tackle structure and device related issues, Address root cause, Good organizational capabilities, Ability to work effectively, Ability to be flexible with job responsibilities, Take the initiative to assume added responsibilities, Interpersonal skills, Customer/co-worker relationships, Demonstrated teamwork skills, Develop good team dynamics, Good multi-tasking skills, Verbal communication skills, Written communication skills
Nice to Have
Knowledge on product and circuit design will be plus
What You'll Do.
Develop best optimum process
Achieve product maturity
Drive best-in-class product maturity
Achieve highest quality
Achieve fastest speed
Achieve fastest cycle of learning
Identify best-known-method holistically
Align best-known-method timely
Implement improvement systematically
Resolve top yield issues
Develop inline visibility
Enable fast yield ramp
Identify best known method
Identify business process
Standardize across network
How You'll Work.
Team & Collaboration
Cross functional team; Collaboration with cross functional team; Collaboration with YE; Collaboration with Device; Collaboration with RDA; Collaboration with Metrology team; Face to face collaboration
Communication Scope
Presentation skills; Verbal communication; Written communication
Full Job Description
**Our vision is to transform how the world uses information to enrich life for all.** Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Frontend Central Product Integration Engineering team strives to deliver leading edge process capability, best-in-class bits per wafer (Yield) with highest quality and fastest speed through innovation and collaboration with cross functional team. With the diversity of technology in DRAM/NAND and geography (TD development sites – Boise/Japan, 5 manufacturing sites – US (F6, ID1), Taiwan (OMT), Japan (F15) and Singapore (F10)), Frontend Central PIE team will be responsible to identify best-known-method holistically, align best-known-method timely and implement improvement systematically across the network. As FE Central Process Integration Senior Engineer, you will be responsible to develop best optimum process to achieve product maturity. Responsibilities and Tasks: * Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning. * In depth knowledge of processes across different loops or functions (FEOL, MOL, CELL, BEOL) to identify best optimum process integration solution to achieve the goal, knowledge on product and circuit design will be plus. * Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to enable fast yield ramp and minimize excursion. * Identify best known method and business process from DRAM/NAND sites and drive for alignment and standardize across network. * Travel to Micron sites as necessary for face
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