Renesas Electronics
Semiconductor
Engineer,PhysicalDesign
Neural analysis suggests this role is
optimal for mid candidates.
“Engineer, Physical Design at Renesas Electronics. Skills: Physical Design, Timing Closure, RTL-GDSII, Physical Verification. Execute physical design flow. Assess risk”
What You'll Achieve.
Meet all deliverables
Industry & Context.
Debug timing violations; Find workaround for problems; Find solutions to problems; Find workaround for tool issues; Find solutions to tool issues
What They're Looking For.
Must Have
2+ years experience in physical design, 2+ years experience in timing closure, Owned Physical Design and taped out at least 1 project, Thorough in PD flows, Thorough in physical verification, Multiple tape out experience, Worked on Synthesis, Worked on timing analysis, Worked on timing closure, Generating ECOs, Scripting skills - Tcl, Scripting skills - perl, Scripting skills - csh, Ability to create methodologies, Ability to automate flows, Worked with foundries/IP vendors, Knowledge of tech files, Knowledge of libraries, Knowledge of IP collaterals, Very good knowledge of timing libraries, Very good knowledge of corners/modes, Very good knowledge of process variations, Very good knowledge of signal integrity issues, Experience in advanced technology nodes (28nm and below), Ability to work in a dynamic environment
Nice to Have
M. Tech in Electronics or Electrical, One project being a first-generation project, Cadence synthesis tools experience, Cadence place and route tools experience, Cadence timing analysis tools experience, Cadence verification tools experience
What You'll Do.
Execute physical design flow
Meet all deliverables
Monitor program from initiation to tapeout
Drive program from initiation to tapeout
Interface with internal stakeholders
Interface with external stakeholders
Achieve alignment across cross-functional teams
Drive block level Place & route
Drive full chip Place & route
Drive block level timing closure
Drive full chip timing closure
Perform Physical verification
Fix Physical verification errors
Work with mixed signal custom design team
Integrate analog macros
Perform Physical verification DRC checks
Perform Physical verification LVS checks
Perform Physical verification Antenna checks
Perform Physical verification IR-EM checks
Debug timing violations
Implement functional ECOs
Implement timing ECOs
Perform formal verification
Work on multi-mode timing closure
Work on multi-corner timing closure
Perform RC extraction
Perform Cross talk analysis
Work closely with RTL design team
Understand constraints
Identify design issues
Find workaround for problems
Find solutions to problems
Find workaround for tool issues
Find solutions to tool issues
Customize Synthesis flows
Customize Synthesis scripts
Customize PNR scripts
Customize STA scripts
Work with foundries on tech files
Work with foundries on libraries
Work with foundries on IP collaterals
Work with IP vendors on tech files
Work with IP vendors on libraries
Work with IP vendors on IP collaterals
How You'll Work.
Team & Collaboration
Interfacing with stakeholders; Alignment across teams; Work with mixed signal team; Work closely with RTL team
Process & Methodology
Program management
Full Job Description
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. We are looking for a motivated Physical Design Engineer to join our Renesas team who can work independently with little or no supervision. Our candidate should be able to execute physical design flow (RTL-GDSII & STA) per planned schedule, assess risk and meet all deliverables. Candidate must monitor and drive the program from initiation to tapeout, interfacing with internal and external stakeholders and achieve alignment across cross-functional teams. Responsibilities: * Drive block level/full chip Place & route and timing closure (Synthesis, PNR, STA and Physical verification). * Closely work with mixed signal custom design team on full chip floorplan to integrate analog macros * Perform Physical verification DRC, LVS, Antenna & IR-EM checks and fixing errors * Run timing analysis, debug t
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