Micron Technology

Semiconductor

Engineer-DRAM,AdvancedDRAMandDevice/CellTechnology

$145–215k ~AI est. Boise, Idaho, United States FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Mid+ candidates.

The Brief

“Engineer- DRAM, Advanced DRAM and Device/Cell Technology at Micron Technology. Skills: DRAM device technology, Device characterization, Failure analysis. Define electrical specifications. Drive electrical specifications”

What You'll Achieve.

Improve yield; Improve quality; Improve cost

Industry & Context.

Semiconductor
Problems you'll solve

Solving hard problems; Root-cause variability; Analyze electrical behavior; Analyze failures

What They're Looking For.

Must Have

MS with 5+ years experience, PhD with hands-on research, Semiconductor device physics expertise, DRAM array characterization experience, Failure analysis experience, Data analysis proficiency, DOE proficiency, Statistical techniques proficiency

Nice to Have

Written communication skills, Verbal communication skills, Experience with process integration, Experience with circuit domains, Experience with architecture domains, Ability to collaborate with multi-functional teams, Problem-solving skills, Ability to communicate technical status to management

What You'll Do.

Define electrical specifications

Drive electrical specifications

Translate product requirements

Implement experiments

Interpret experiments

Optimize cell performance

Optimize access device performance

Develop integration schemes

Define characterization methodologies

Develop physical models

Develop electrical models

Identify performance limiters

Identify yield limiters

Identify reliability limiters

Create stress methodologies

Improve stress methodologies

Evaluate device reliability

Establish design margins

Analyze array-level behavior

Root-cause variability

Optimize distributions

Collaborate cross-functionally

Translate device insights

Enable memory solutions

How You'll Work.

Team & Collaboration

Cross-functionally with process integration; Cross-functionally with design; Cross-functionally with product engineering

Communication Scope

Technical status reporting

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the R&D DRAM Device and Cell Technology Group at Micron, working at the heart of future memory scaling in an industry‑leading 300mm R&D facility. We explore new device concepts, push the limits of DRAM cell performance, and turn deep physics understanding into manufacturable technology. If you enjoy learning fast, solving hard problems, and collaborating across process areas, this team delivers! In this role, you will play a critical part in defining and validating future DRAM device and cell technologies. As a Device Engineer, you will characterize memory arrays, analyze electrical behavior and failures, and influence process and material decisions that directly impact yield, quality, and performance. Your work will shape the electrical foundation of next‑generation DRAM products. **Responsibilities:** * Define and drive electrical specifications for DRAM, Advanced DRAM and emerging memory technologies, translating product requirements into device-level targets for performance, reliability and scaling * Design, implement, and interpret experiments to optimize cell and access device performance. This includes running materials experiment, developing new integration schemes and defining new characterization methodologies * Develop physical and electrical models (TCAD and compact modeling) to identify performance, yield and reliability limiters, using advanced materials characterization, device physics insight, and statistical data analysis * Create and or improve stress methodologies to evaluate device reliability (e.g., TDDB, leakage, variability, endurance) and establish robust design margins. * Analyze array-level behavior using probe, parametric, and ba

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