Black Semiconductor
semiconductor
Electronic-PhotonicsICMaskDataPreparation&GDSDataIntegration-SMTS
Neural analysis suggests this role is
optimal for Senior candidates.
“Electronic-Photonics IC Mask Data Preparation & GDS Data Integration - SMTS at Black Semiconductor. Skills: Electronic-Photonics IC Mask Data Preparation, GDS Data Integration, Tape-out flow ownership, Mask Data Preparation (MDP), GDSII/OASIS, DRC/LVS/ERC verification, Calibre, Synopsys ICV. Own the complete tape-out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, and rule file maintenance for PIC-EIC integration and new process nodes. Lead GDS and reticle”
What You'll Achieve.
Own the complete tape-out flow; Drive EIC+PIC DfX co-integration; ensure seamless alignment between design, fabrication, testing, and packaging requirements; Lead GDS and reticle-to-fab delivery; ensure all layers, formats, and data structures comply with fab specifications; Drive DFM and DFT integration through yield optimization; support first-silicon bring-up; continuous improvement of MDP best practices
Industry & Context.
hotspot mitigation; layout optimization; first-silicon debug; layout-based failure analysis
What They're Looking For.
Must Have
MS or PhD in Electrical Engineering, Physics, or a related field, 5+ years of experience in semiconductor or photonics tape-out, layout integration, and Mask Data Preparation (MDP), expertise in GDSII/OASIS, DRC/LVS/ERC verification flows, industry-standard tools such as Calibre and Synopsys ICV, MDP job deck authoring and JDV (Jobdeck View), Hands-on experience with production tape-out flows including DFM, DFT, ESD, seal ring/kerf, and RDL layout implementation, Familiarity with OPC flows for advanced photonics or CMOS nodes, experience coordinating with mask shops and foundry partners
Nice to Have
Experience with Photonic IC technologies (Si, SiN, etc. ), graphene or 2D-material integration, RF photonics, photonic/electronic co-design EDA tools such as Cadence EPIC or Lumerical, Background in mask shops or EDA software environments (e. g. Synopsys, Siemens, Cadence, Toppan, Photronics, Compugraphics, Tekscend)
What You'll Do.
Own the complete tape-out flow including Mask GDS/MDP integration
DRC/LVS/ERC verification
and rule file maintenance for PIC-EIC integration and new process nodes
Lead GDS and reticle-to-fab delivery
formal mask release activities
and ensure all layers
and data structures comply with fab specifications
Drive DFM and DFT integration through yield optimization
and implementation of scan chains
and optical probe structures within GDS
Design and integrate special GDS structures including kerf
metrology & PCM structures
ESD protection layouts
and RDL packaging interfaces
Maintain GDS version control and audit-trail archiving
support first-silicon debug
layout-based failure analysis
and continuous improvement of MDP best practices
How You'll Work.
Team & Collaboration
Drive EIC+PIC DfX co-integration across a 300 mm graphene photonics platform, ensuring seamless alignment between design, fabrication, testing, and packaging requirements throughout the development cycle; Act as the primary interface between mask shops, foundry lithography/metrology teams, EDA vendors, and cross-functional analog, digital, packaging, and reliability teams across global regions
Full Job Description
About us We see the semiconductor industry as a realm of possibility. We see opportunity. We see the profound impact that our graphene solutions will have in transforming the industry. We invite you to join us in driving change with our fundamentally human-centered approach, uniting bright minds around a shared vision. The vision is: Prove to everybody that you can make a fundamental change. Prove with your knowledge and skills how things can be done differently. Together, we can change the paradigm of how the world connects About our technology The semiconductor industry’s growing demand for more powerful chips with higher bandwidth and lower power finds its solution in our technology. We connect chips to high-throughput, low-delay computing networks. The key lies in harnessing the physical properties of graphene to combine electronic computing with photonic communication, allowing countless chips to interact almost as if they were one. Our graphene photonic innovation increases computing power and efficiency to a new order of magnitude In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solution The Role We are seeking an experienced Electronic-Photonics IC Mask Data Preparation & GDS Data Integration – SMTS to take technical ownership of the complete tape-out flow — from GDS database integration and mask data preparation through mask release, first silicon bring-up, and post-tapeout support. In this role, you will drive EIC+PIC DfX co-integration (Design for Functionality, Manufacturing, Test, Packaging, and Reliability) across a 300 mm graphene photonics platform, ensuring seamless alignment between design, fabrication, testing, and packaging requirements throughout the development cycle. To join our team, you should be excited to: - Own the complete tape-out flow including Mask GDS/MDP integration, DRC/LVS/ERC verification, final mask sign-off, an
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