Western Digital
Data Storage
EDACADEngineer
“EDA- CAD Engineer at Western Digital. Skills: EDA CAD engineering, design flow automation, Analog IC design, Mixed-signal IC design, Physical Verification flows, Scripting languages, EDA tool integration and support. Develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.. Design, implement, and maintain robust CAD flows and methodologies for analog and mixed-signal IC design (spanning simulation, physical design, verification and familiarity with R”
What You'll Achieve.
Develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.; Maximize engineering efficiency.
Industry & Context.
Problem solvers; Troubleshoot design flow bottlenecks, license issues, and tool crashes
What They're Looking For.
Must Have
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field., Minimum 0-5+ years of experience in an EDA CAD engineering or design flow automation role., Analog or Mixed Signal EDA Tool Knowledge: Hands-on experience with industry-standard tools., Understanding of modern semiconductor manufacturing processes and physical design rules., Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A, Proficiency in scripting languages such as Python, Tcl, Perl, or Shell scripting (bash/csh)., Working knowledge of Linux/Unix environments, compute grid/scheduler management (e. g. , LSF, Slurm, Grid Engine), and version control systems (e. g. , Git, Perforce).
What You'll Do.
Develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.
and maintain robust CAD flows and methodologies for analog and mixed-signal IC design (spanning simulation
verification and familiarity with RTL/synthesis).
Run and Debug Physical Verification flows including DRC
ERC and Antenna Checks
Develop custom scripts and internal utilities to automate repetitive design tasks
improve tool interoperability
and maximize engineering efficiency.
and integrate industry-standard EDA tools (Cadence
Siemens/Mentor Graphics) into our infrastructure.
Provide technical support to the design teams.
Monitor and optimize compute resource utilization
Troubleshoot design flow bottlenecks
Act as the primary technical liaison with EDA tool vendors to resolve software bugs
evaluate new features
and manage license compliance.
Maintain design data management (revision control) systems and ensure clean
reproducible workspace environments
Coordination of a Split-Fab Design environment for WD PDKs (for Memory Array Layers) and a CMOS Foundry PDK (for Operational Circuitry)
Development of EDA Tool Design Rules for WD’s Memory Array Layers
Defining and executing the split-fab tape out flow
How You'll Work.
Team & Collaboration
Part of a multi-functional team; Provide technical support to the design teams
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