Micron Technology
Semiconductor
DMTSDigitalDesignEngineer/ChipLead
Neural analysis suggests this role is
optimal for Lead candidates.
“DMTS Digital Design Engineer / Chip Lead at Micron Technology. Skills: Digital Design, Chip Lead, RTL Design, Timing Closure. Define top-level chip architecture. Partition responsibilities across IP blocks”
What You'll Achieve.
Carry high-speed interface innovations to tape-out; Achieve clean handoff to foundry; Accelerate follow-on chip development
Industry & Context.
Debug; Timing closure; PPA optimization
What They're Looking For.
Must Have
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field, 10+ years of ASIC/digital design experience, Prior tape-out in a chip lead, design lead, or senior designer role, Expert-level proficiency in SystemVerilog RTL design, Experience with logic synthesis tools, Experience with static timing analysis, Proficiency with RTL simulation and debug tools, Solid understanding of CDC analysis methodologies, Demonstrated experience integrating hard and soft IP blocks, Ability to work effectively as a technical lead, Written communication skills
Nice to Have
Experience with high-speed PHY architectures, Familiarity with I2C management bus architecture, Familiarity with Eye Monitor control logic, Familiarity with PRBS-based error counting implementations, Experience with DFT strategy definition, Familiarity with OTP/fuse-based trim and calibration architectures, Prior experience in a small team or startup-like environment
What You'll Do.
Define top-level chip architecture
Partition responsibilities across IP blocks
Integrate hard macros and soft IP
Author synthesizable RTL
Review synthesizable RTL
Maintain synthesizable RTL
Develop chip-level timing constraints
Define clock domain crossing strategy
Provide timing budgets per block
Drive logic synthesis
Optimize for PPA targets
Define interfaces between PHY and IP
Manage IP integration agreements
Drive tape-out checklist sign-off
Coordinate design handoff to foundry
Author architecture specifications
Author block-level design specifications
Author interface control documents
Capture design decisions
Document lessons learned
Document architectural rationale
How You'll Work.
Team & Collaboration
Technical anchor of team; Coordinate across teams; Vendor coordination
Communication Scope
Written communication; Design documentation
Process & Methodology
Tape-out ownership
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Digital Design Engineer / Chip Lead, you will be the technical anchor of a small, senior team spanning analog design, layout, silicon characterization, physical design, and verification — united around the goal of carrying high-speed interface innovations from architecture to tape-out. This is a full-ownership role. You will define top-level chip architecture, author and maintain synthesizable RTL for all soft IP control blocks, own timing constraints and clock domain crossing strategy, drive synthesis and tape-out sign-off, and produce the design documentation that serves as the authoritative reference for the team. The program integrates a fully custom analog PHY alongside digital control functions — providing a technically rich chip-lead scope that spans hard macro integration, third-party IP management, and original RTL design. This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and design complexity. **Responsibilities** * **Chip Architecture & Integration:** Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP. * **RTL Design:** Author, review, and maintain synthesizable RTL (SystemVerilog) for all soft IP control blocks, CSR/register file, clocking control logic, and top-level integration. * **Timing Closure Leadership:** Develop and o
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