Astera Labs
AI Infrastructure
Director,DigitalCompute&PowerOptimization
Neural analysis suggests this role is
optimal for Director candidates.
“Director, Digital Compute & Power Optimization at Astera Labs. Skills: Digital Design Engineering, RTL Development, SerDes DSP Design, High-speed Protocols. Drive high-speed connectivity solutions. Build and lead a team”
What You'll Achieve.
Deliver the micro-architecture and implementation; Unlock the full potential of modern AI; Deliver end-to-end scale-up, and scale-out connectivity; Deploy tailored architectures
Industry & Context.
equalizer optimization for power and area efficiency; Think and act fast with the customer in mind!
Authorized to work in Canada, start immediately
What They're Looking For.
Must Have
academic and technical background in electrical engineering, Bachelor's degree in EE, 10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications, 5+ years’ experience managing a team of RTL design engineers, Professional attitude, ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, work with minimal guidance and supervision, Entrepreneurial, open-mind behavior, can-do attitude, Think and act fast with the customer in mind!, Authorized to work in Canada, start immediately, Hands-on, thorough knowledge of high-speed DPSs and SerDes equilizers, Hands-on, thorough knowledge of high-speed protocols like CXL/PCIe, Ethernet, or DDR, Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc, Experience with Cadence and/or Synopsys digital design tools/flows, Experience with scripting and automation, methodology background, Good knowledge of design for test (DFT), stuck-at and transition scan test insertion, Familiarity with UVM based design verification, Silicon bring-up and debug expertise, Small-geometry CMOS (≤28nm) design
Nice to Have
Master's degree, Firmware development with C-language, scripting with Python or other equivalent programming languages, Development/support for PCIe or Ethernet Switch products
What You'll Do.
Drive high-speed connectivity solutions
Build and lead a team
Deliver micro-architecture
Deliver implementation
Block-level verification
Optimize for power and area efficiency
Support silicon products
Manage a team of RTL design engineers
Prepare for customer meetings
Work with minimal guidance
Develop custom connectivity solutions
How You'll Work.
Team & Collaboration
Collaborating with hyperscalers; Collaborating with ecosystem partners; Work with product team; Work with minimal guidance and supervision
Communication Scope
plan and prepare for customer meetings in advance
Process & Methodology
Plan and prepare for customer meetings in advance, Prioritize a dynamic list of multiple tasks
Full Job Description
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs. The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency. The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR. Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred. 10+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. 5+ years’ experience managing a team of RTL design engineers. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guid
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