TechBiz Global
Technology
DFT&Post-SiliconValidation
Neural analysis suggests this role is
optimal for experienced candidates.
“DFT & Post-Silicon Validation at TechBiz Global. Skills: DFT, Post-Silicon Validation, SoC, SiP. Lead engineering teams. Mentor engineering teams”
What You'll Achieve.
Deliver high-quality SoCs; Deliver high-performance SoCs; Deliver high-quality SiPs; Deliver high-performance SiPs; Mass production
Industry & Context.
Root cause analysis
What They're Looking For.
Must Have
Bachelor's, Master's, or PhD, Multiple tape-outs experience, Post-silicon test optimization, Yield analysis experience, Define test strategies, RTL and testbench development, SystemVerilog and Verilog proficiency, Scripting skills
Nice to Have
Tessent and SSN methods experience, Advanced technology nodes experience
What You'll Do.
Lead engineering teams
Mentor engineering teams
Provide technical direction
Foster continuous improvement
Define DFT architectures
Implement DFT architectures
Improve debug capabilities
Improve manufacturability
Optimize DFT methodologies
Develop test strategies
Implement test strategies
Define automated test solutions
Develop automated test solutions
Consider chiplet complexities
Work with design teams
Work with validation teams
Work with packaging teams
Work with operations teams
Work with product management
Explore new DFT methodologies
Implement new DFT methodologies
Explore new manufacturing processes
Implement new manufacturing processes
Lead cost reduction initiatives
Lead efficiency improvement initiatives
Lead quality enhancement initiatives
How You'll Work.
Team & Collaboration
Cross-functional teams; External IP providers; EDA vendors; Internal teams; Design teams; Validation teams; Packaging teams; Operations teams; Product management
Full Job Description
At TechBiz Global , we are providing recruitment service to our TOP clients from our portfolio. We are currently looking for a DFT & Post-Silicon Validation to join one of our clients' team Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production. Key Responsibilities * Leadership & Team Management * Lead and mentor the DFT and Post-Silicon engineering teams to drive innovation and efficiency. * Provide technical direction, ensuring alignment with organizational goals. * Foster a culture of continuous improvement and collaboration. * DFT Strategy & Execution * Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability. * Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces. * Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield. * Test Development & Implementation * Develop and implement test plans and test strategies at silicon, package, and system levels. * Define and develop automated test solutions for production and characterization. * Ensure test coverage for all product development stages, from pre-silicon to mass production. * Guarantee high yield on the final solution while considering chiplet complexities. * Cross-Functional Collaboration * Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability. * Collaborate with product management to ensure alignment with customer requirements and timelines. * Process Improvement & Innovation * Contin
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