Etched
AI inference system
DFTInternSummer2027
“DFT Intern - Summer 2027 at Etched. Skills: DFT flow automation, chip-level regression, DFT verification, MBIST, Scan, BSCAN, SSN simulations, ATPG fault models. review and refine DFT flow automation to support chip-level regression on Caelius. contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations)”
Industry & Context.
What They're Looking For.
Must Have
Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field, Familiarity with a hardware description language (Verilog or SystemVerilog), Exposure to ASIC or SoC design concepts, Familiarity with digital logic design fundamentals, Familiarity with standard ASIC design flow steps (synthesis, STA, DFT), Familiarity with scripting in Python, Tcl, or another language, Ability to learn quickly about transformers and other aspects of modern artificial intelligence
Nice to Have
Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression, Experience with Tessent or similar DFT tooling, Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF), Exposure to DFT flow automation or regression infrastructure, Familiarity with clocking and reset schemes
What You'll Do.
review and refine DFT flow automation to support chip-level regression on Caelius
contribute to DFT verification (including MBIST
develop flows for various ATPG fault models
How You'll Work.
Team & Collaboration
work across frontend and backend design teams
Applying for this DFT Intern - Summer 2027 role?
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