Etched
AI inference system
DFTIntern-Fall2026
Neural analysis suggests this role is
optimal for Entry candidates.
“DFT Intern - Fall 2026 at Etched. Skills: DFT, ASIC design, Verilog, SystemVerilog, Python, Tcl. review and refine DFT flow automation to support chip-level regression on Caelius. contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations)”
Industry & Context.
12-week paid internship, Generous housing support for those relocating, Daily lunch and dinner in our office, Based at our office in San Jose, CA, Direct mentorship from industry leaders and world-class engineers
What They're Looking For.
Must Have
Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field, Familiarity with a hardware description language (Verilog or SystemVerilog), Exposure to ASIC or SoC design concepts, Familiarity with digital logic design fundamentals, Familiarity with standard ASIC design flow steps (synthesis, STA, DFT), Familiarity with scripting in Python, Tcl, or another language, Ability to learn quickly in a fast-paced, high-autonomy environment, Ability to learn quickly about transformers and other aspects of modern artificial intelligence
Nice to Have
Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression, Experience with Tessent or similar DFT tooling, Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF), Exposure to DFT flow automation or regression infrastructure, Familiarity with clocking and reset schemes
What You'll Do.
review and refine DFT flow automation to support chip-level regression on Caelius
contribute to DFT verification (including MBIST
develop flows for various ATPG fault models
How You'll Work.
Team & Collaboration
work across frontend and backend design teams
Full Job Description
About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. You may be a good fit if you have - Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field. - Familiarity with a hardware description language (Verilog or SystemVerilog) - Exposure to ASIC or SoC design concepts - Familiarity with digital logic design fundamentals - Familiarity with standard ASIC design flow steps (synthesis, STA, DFT) - Familiarity with scripting in Python, Tcl, or another language - Are able to learn quickly about transformers and other aspects of modern artificial intelligence Strong candidates may also have experience with - Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression - Experience with Tessent or similar DFT tooling - Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF) - Exposure to DFT flow automation or regression infrastructure - Familiarity with clocking and reset schemes We encourage you to apply even if you do not believe you meet every si
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