DFTEngineer(DesignforTestability)-Staff

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. **Responsibilities will include, but are not limited to:** * Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. * Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. * Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. * Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. * Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. * Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified. * Collaborate with external partners and customers to align on custom DFT interfaces and security requirements when applicable. * Support silicon bring‑up, debug,