Samsung Austin Semiconductor
Semiconductor
DeviceIntegrationEngineer
Neural analysis suggests this role is
optimal for Mid candidates.
“Device Integration Engineer at Samsung Austin Semiconductor. Skills: Device integration, Process optimization, Yield analysis. Perform split lot design and DOE analysis. Collaborate with integration and module teams”
What You'll Achieve.
Enhance transistor performance; Target transistor performance; Improve device reliability; Improve yield learning; Improve manufacturability; Deliver industry-leading device performance at the 2nm node and beyond; Solve systematic yield, performance, or reliability issues; Ensure targeting of transistor focused ET trends to Customer/Product specifications; Manage Parametric Yield and Wafer Acceptance Electrical Test; Improve process; Accelerate yield ramp
Industry & Context.
Analysis skills; Electrical device characterization; Yield analysis; Data mining; DOE; SPC; Root cause analysis; Ability to reason logically; Make sound decisions; Consider alternative and diverse perspectives; Deal with ambiguity
U. S. Export Control Compliance, May require access to information subject to U. S. export control laws, Applicants must be authorized to access such information or eligible for government authorization, Not disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity
What They're Looking For.
Must Have
Bachelors of Science or Engineering (Electrical, Computer, Chemical, Material Science, or related areas), 3-8 years of experience relevant experience, Understanding of the interactions between process and Electrical test, Knowledge of process flow, Familiarity with unit processes including thin films deposition, etch, diffusion, wet process, CMP, lithography, implant, anneal, etc., Analysis skills, including electrical device characterization, yield analysis, data mining, DOE, and SPC, Excellent communication, documentation and presentation skills, Capable of shifting focus and changing priorities - dealing with ambiguity, Demonstrated ability to meet deadlines and commitments while managing multiple priorities, Ability to reason logically and make sound decisions, Ability to consider alternative and diverse perspectives, Ability to communicate effectively both orally and in writing, Ability to remain poised under all circumstances, Ability to interact effectively with people in a positive manner that engenders confidence and trust, Ability to complete assigned tasks without direct supervision, Ability to exercise independent judgment and make decisions, Ability to work effectively and efficiently in high stress and conflict situations, Good communication and interpersonal skills
Nice to Have
Masters or PhD, 5+ years of industry experience, Spotfire experience, SPICE modeling and simulation experience
What You'll Do.
Perform split lot design and DOE analysis
Collaborate with integration and module teams
Resolve device-process interactions
Define optimization paths
Lead root cause analysis for device failures
Drive corrective actions
Drive Task Force Teams
Solve systematic yield
or reliability issues
Ensure targeting of transistor focused ET trends
Perform timely root cause study
Analyze process interactions
Owns Parametric Yield and WAT management
Support unit process team
Evaluate device impact
Generate written reports and oral presentations
Conduct Local Layout Effects analysis
Characterize and mitigate transistor performance variability
Provide paths to module and fab engineering
Feed findings into design rule definition
Feed findings into SPICE models
Lead Material to Hardware Correlation task force
Link upstream material and process metrology data
Enable predictive process control
Accelerate yield ramp
How You'll Work.
Team & Collaboration
Collaborate closely with integration, process module, Fab engineering and DFM teams; Collaborate with integration and module teams; Provide paths to module and fab engineering
Communication Scope
Excellent communication; Oral presentations; Written reports; Communicate effectively both orally and in writing
Process & Methodology
Drive Task Force Teams
Full Job Description
**About Samsung Austin Semiconductor** Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At SAS, we are Innovating Today to Power the Devices of Tomorrow. **Come innovate with us!** **Position Summary** We are seeking a highly experienced Device Engineer to join our cutting-edge 2nm Gate-All-Around (GAA) device engineering team. In this individual-contributor role, you will be responsible for process – device co-optimization to enhance transistor performance and targeting, reliability, yield learning and manufacturability GAA technology derivatives. This role will collaborate closely with integration, process module, Fab engineering and DFM teams, to deliver industry-leading device performance at the 2nm node and beyond and works on problems of diverse scope or on advanced assignments that require considerable judgment and initiative. Minimal supervision is required unless major decisions are made where the supervisor is needed and may provide guidance to non-exempt and exempt personnel. **Role and Responsibilities** **Here’s What You’ll Be Responsible For:** * Perform split lot design and DOE analysis to identify key process knobs impacting device performance and yield. * Collaborate with integration and module teams to resolve device-process interactions and define optimization paths. * Lead root cause analysis for device failures and non-conformances; drive corrective actions across fab operations. * Drive Task Force Teams to solve systematic yield, performance, or reliability issues. * Ensure targeting of transistor focused Electrical Test (ET) trends to Customer/Product specifications and perform timely root cause study to shifts or abnormality. Analyze process interactions (inline metrology, FDC, etc.) to ET while also understanding ET data effect on Parametric Yield. * Owns Parametric Yield and Wafer Acceptance Electrical Test (WAT) management for one or more Customer A
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