DesignLayoutEngineer

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has transformed innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are redefining how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s DRAM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. **Responsibilities:** * Design and development of analog, mixed-signal, custom digital block and full chip level integration support. * Perform layout verification like LVS/DRC/Antenna, quality check and documentation. * Responsible for on-time delivery of block-level layouts with acceptable quality. * Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. * Effectively communicating with Global engineering teams to assure the success of layout project. **Minimum Qualification:** * Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET). * BE or MTech in Electronic/VLSI Engineering, or related. * Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. * Should have hands on experience in creating layout of critical blocks such as Temperature sensor,