Cadence

electronic design

DesignEngineeringArchitect

Cork, Ireland FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Design Engineering Architect at Cadence. Skills: RTL design, SoC architecture, Technical leadership. Technical leadership of complex IP. Collaborate with system architects”

What You'll Achieve.

Deliver software, hardware and IP that turn design concepts into reality; Enable customers to tackle IP-to-SoC development; Enable customers to focus on product differentiation; Reduce time to volume; Deliver industry leading IP solutions; Enable customers to be successful

Industry & Context.

electronic design
Eligibility Requirements

Travel: <10%

What They're Looking For.

Must Have

Degree in Electrical/Electronic Engineering, microelectronics, or a related discipline, 15-20 years’ experience in microelectronics industry, Expert in Verilog/SystemVerilog RTL design, Expert in front-end design tools covering LINT, synthesis, CDC/RDC analysis, Experience of SoC architecture and development, Experience of technical team leadership, Excellent oral and written English

Nice to Have

Experience of Metric Driven Verification (MDV) and UVM, Experience of industry standard protocols such as AXI, CHI-C2C & CXS. B, Experience of quality processes, such as ISO-9001 & ISO-26262

What You'll Do.

Technical leadership of complex IP

Collaborate with system architects

Define architecture and specifications

Hands-on leadership of RTL development

Contribute to planning of activities

Leadership of cross-functional meetings

Support customer meetings

Participate in Technical Review Meetings

Represent Cadence in Standards Body Working Groups

Present at Industry Conference

How You'll Work.

Team & Collaboration

Collaborate with system architects; Leadership of cross-functional technical meetings with Analog & Software counterparts

Communication Scope

Excellent oral and written English; Communicate complex concepts clearly and thoroughly

Process & Methodology

Planning of activities and milestones

Full Job Description

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.** **Job Title: Design Engineering Architect** **Location: Cork/Dublin, Ireland** **Reports to: Design Engineering Director** **Job Overview:** The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. The Cadence IP Vision is to deliver industry leading IP solutions to enable our customers to be successful across these fast-moving application spaces. The Design Engineering Architect will be based in Cork, as part of an experienced Controller IP Team with long established IP development sites in Europe, US and India. **Job Responsibilities:** * Technical leadership of complex IP such as UCIe, Ethernet, HBM and PCIe. * Collaborate with system architects and product managers to define the architecture and specifications on standards such as UCIe, considering factors such as data rate, power consumption, and compatibility with industry standards. * Hands-on leadership of RTL development from micro-architecture definition to IP sign-off for general release. * Cont

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