Micron Technology
Technology
DesignArchitecture,PrincipalEngineer
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optimal for Principal candidates.
“Design Architecture, Principal Engineer at Micron Technology. Skills: HBM Design Architecture, AI memory, System environments. Research and synthesize emerging trends. Lead HBM architecture analysis”
Industry & Context.
System-level trade-offs
What They're Looking For.
Must Have
Bachelor’s or Master’s degree, Understanding of materials and technology challenges, Experience with memory subsystem design, Multi-disciplinary experience in Fab & Foundry space
Nice to Have
Exposure to electrical, materials challenges, Ability to turn research and model outputs into technical recommendations
What You'll Do.
Research and synthesize emerging trends
Lead HBM architecture analysis
Define bandwidth/latency targets
Translate workload and system data
Develop and maintain simulation frameworks
Model AI cluster performance
Validate models against benchmarks
Build and apply performance models
Guide architectural decisions
Create and curate trend dashboards
Define architectural intercept opportunities
Align on requirements
How You'll Work.
Team & Collaboration
Architects and senior engineers; DTPCO, Design, and Product/System teams
Full Job Description
**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. **HBM Design Architecture — Principal Engineer** **Role Overview** We are seeking a highly motivated **HBM Design Architecture Engineer (Principal Engineer)** to drive exploration and definition of next‑generation AI memory and system environments. In this role, you will analyze emerging infrastructure trends, build performance models, and develop/extend tooling that informs HBM architecture decisions and system‑level trade‑offs. You will work closely with architects and senior engineers across DTPCO, Design, and Product/System teams to translate AI workload requirements into actionable memory subsystem and architectural intercept strategies. **Key Responsibilities** You will own and contribute to projects such as: * **Research and synthesize emerging trends** in compute, networking, and storage infrastructure to anticipate how future AI systems will evolve. * **Lead HBM architecture analysis** by defining bandwidth/latency targets, identifying constraints, and translating workload and system data into actionable memory requirements. * **Develop and maintain simulation frameworks** to model AI cluster performance and memory subsystem behavior; validate models against internal and external benchmarks. * Build and apply **first‑order performance models** spanning HBM bandwidth/latency, GPU/CPU interactions, and memory hierarchy trade‑offs to guide architectural decisions. * Create and curate **trend dashboards** using CSP benchmarks and industry datasets; communicate insights, assumptions, and sensitivity analyses to stakeholders. * Partner across DTPCO, Design, and Product/System teams to define **architectural intercept opportunities** , align on requirements, an
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