Tenstorrent
AI technology
CPUCoreDesignVerificationTestGeneratorLead
“CPU Core Design Verification Test Generator Lead at Tenstorrent. Skills: CPU Core Design Verification, Test Generator Development, RISC-V Architecture, Out-of-order CPU Microarchitecture. Own CPU core-level test generator development and verification strategy. Shape how out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior”
Industry & Context.
solving hard problems
Offer of employment contingent upon the applicant being eligible to access U. S. export-controlled technology, Offer may be contingent upon citizenship/permanent residency status or ability to obtain prior license approval from the U. S. Commerce Department or applicable federal agency due to U. S. export laws
What They're Looking For.
Must Have
8+ years in CPU design verification, test generation, or closely related CPU validation work, Led development of test generators for x86, ARM, or RISC-V ISA environments, Understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture, Comfortable building tools, stimulus, and automation that scale verification across large CPU programs, Communicate clearly across design, DV, architecture, emulation, and post-silicon teams, Eligible to access U. S. export-controlled technology
What You'll Do.
Own CPU core-level test generator development and verification strategy
Shape how out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior
Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores
Own generator strategy
and methodology for ISA and microarchitectural verification
Develop directed and randomized stimulus that targets architectural corner cases
instruction interactions
and complex CPU behavior
Support RISC-V certification work
including test content
Guide a small team of 4-5 engineers while staying hands-on with implementation
and verification execution
How You'll Work.
Team & Collaboration
Communicate clearly across design, DV, architecture, emulation, and post-silicon teams; Guide a small team of 4-5 engineers
Communication Scope
Communicate clearly across design, DV, architecture, emulation, and post-silicon teams
Process & Methodology
Own generator strategy, infrastructure, and methodology, Guide a small team of 4-5 engineers
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