NVIDIA
Semiconductor
ChipLead,SiliconCoDesignGroup
“Chip Lead, Silicon Co-Design Group at NVIDIA. Skills: Chip Lead, technical lead, end-to-end understanding of SoC and ASIC architecture, expertise in at least one subsystem (HBM, SerDes, power and thermal, or packaging), silicon-level impact, guiding technical decisions across functional boundaries, translating sophisticated silicon issues into clear options for executive audiences. Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.. Co-lead pro”
What You'll Achieve.
deliver chips that change what is possible; The program runs cleaner because you are on it!; faster bring-up; fewer escapes; yield recovery; methodology contributions
Industry & Context.
help resolve the toughest multi-functional bugs; translating ambiguous, multi-team symptoms into root-cause closure; guide the mitigations; turning ambiguous, multi-team failure modes into root-cause closure
What They're Looking For.
Must Have
BS or MS (or equivalent experience) in Electrical or Computer Engineering, over a decade of proven track record in post-silicon bring-up, validation, or system integration leadership at a major semiconductor company, work on multiple shipped silicon products, 12+ years of experience, end-to-end understanding of SoC and ASIC architecture, recognized expertise in at least one subsystem such as HBM, SerDes, power and thermal, or packaging, Specific examples of silicon-level impact, such as faster bring-up, fewer escapes, yield recovery, or methodology contributions, turning ambiguous, multi-team failure modes into root-cause closure with reusable workarounds and write-ups, A track record of guiding technical decisions across functional boundaries without direct reporting authority, translating sophisticated silicon issues into clear options for executive audiences
Nice to Have
Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC, Patents, conference papers, invited talks, or recognized contributions to silicon validation, post-silicon debug, or co-design integration are a plus, A history of building and sharing technical methodology beyond a single program — reusable playbooks, debug frameworks, or standards adopted by other teams, Hands-on debug experience with HBM, high-speed I/O, power and thermal, or packaging is welcome, Comfort working through ambiguity with globally distributed teams, a habit of surfacing the right risks and recommendations to leadership without being asked, using AI tools to lift team velocity, not just personal productivity
What You'll Do.
Serve as the single technical point of contact for multi-functional decisions
Co-lead program-level feature integration from chip to system
surfacing inter-function dependencies and guiding them to resolution.
Help resolve the program’s hardest multi-functional bugs by translating ambiguous
multi-team symptoms into root-cause closure on areas such as HBM
Steward the qualification playbook. When the playbook does not fit a situation
guide the mitigations and capture the lessons as reusable methodology for other SSG programs.
Shape the program’s technical narrative by surfacing key risks
and mitigations as decision-ready options for executive leadership.
Mentor Chip Leads on adjacent silicon programs and contribute to SCG-wide methodology through post-mortems and write-ups.
Lead the program’s Critical Debug and SCG Technical Execution forums
and represent the chip externally with early insight into technical risks.
How You'll Work.
Team & Collaboration
partner across design, validation, software, and manufacturing; Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs.; Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution.; Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure; guiding technical decisions across functional boundaries without direct reporting authority; Comfort working through ambiguity with globally distributed teams
Communication Scope
translating sophisticated silicon issues into clear options for executive audiences; Shape the program’s technical narrative
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