Hewlett Packard Enterprise
edge-to-cloud
ASICVerificationEngineer
Neural analysis suggests this role is
optimal for Mid candidates.
“ASIC Verification Engineer at Hewlett Packard Enterprise. Skills: ASIC Verification, SystemVerilog, UVM. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems”
What You'll Achieve.
sign off them for tape-out
Industry & Context.
Analytical Thinking; Critical Thinking; Group Problem Solving; problem solving; ASIC debugging
Onsite work expectation
What They're Looking For.
Must Have
ASIC Verification using SystemVerilog, MSEE or BSEE is required with 3 plus years of experience
Nice to Have
constrained-random verification, verification methodology like OVM/VMM/UVM, Perl/Tcl scripting, networking protocols such as Ethernet, ASIC debugging skills
What You'll Do.
Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology
and deliver verification suites/tests for ASICs that enable faster
Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage
functional coverage and Gate level simulation
Python and/or shell scripts to improve current verification infrastructure/methodology
How You'll Work.
Team & Collaboration
Work closely with logic designers to resolve bugs; Work closely with software developers to assist in software and bring-up development
Communication Scope
Active Listening
Process & Methodology
Action Planning, Long Term Planning
Full Job Description
ASIC Verification Engineer This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. **Who We Are:** Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. **Job Description:** Job Description **Networking** is an HPE Company, and a leading provider of next-generation network access solutions for the mobile enterprise. Helping some of the largest companies in the world modernize their networks to meet the demands of a digital future, Aruba is redefining the “Intelligent Edge” – and creating new customer experiences across intelligent spaces and digital workspaces. Join us redefine what’s next for you. **What you 'll do:** * You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. * Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%) * Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/Xcelium) to perform this activity. (25%) * Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%) * Work closely with logic designers to resolve
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