Intel

AnalogMixedSignalDesignEngineer

CA$130–183k Canada FULL TIME Remote Friendly
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Analog Mixed Signal Design Engineer at Intel. Skills: analog mixed signal design, static timing analysis, mixed-signal verification, analog circuit design, behavioral modeling, scripting. Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces. Drive timing optimization and constraint development for complex mixed-signal systems”

What You'll Achieve.

drive timing closure across analog-digital interfaces; supporting comprehensive design verification activities that directly impact Intel's industry-leading products; accelerate silicon success; ensuring robust timing closure across analog-digital interfaces; drive timing optimization; optimize circuit performance; improve simulation accuracy and efficiency; deliver measurable business impact across Intel's product and foundry businesses

Industry & Context.

Problems you'll solve

analytical and problem-solving skills; Investigate and resolve complex issues in analog testbenches and mixed-signal simulations; Root-cause analysis of pre-silicon design challenges with systematic corrective action implementation

Eligibility Requirements

must live and work from the country specified in the job posting, in which Intel has a legal presence, Due to legal regulations, remote work from any other country is unfortunately not permitted

What They're Looking For.

Must Have

2+ years of experience with mixed signal verification and driving methodology changes and initiatives, 2+ years of experience in scripting languages such as Python for automation purposes

Nice to Have

Post Graduate degree in Electrical or Computer Engineering or in a STEM related field, Experience working within mixed signal systems like SerDes or PLLs, Experience with static timing analysis and analog circuit designs, Experience with Cadence ADE for running simulations and debugging testbenches, Experience with script development and automation using AI, Experience with mixed-signal design principles, including interfaces between analog and digital domains, analytical and problem-solving skills, alongside effective team collaboration capabilities, Experience with analog behavioral modeling (Verilog-A, SystemVerilog, etc. ) is a plus

What You'll Do.

Lead static timing analysis (STA) execution for mixed-signal designs

ensuring robust timing closure across analog-digital interfaces

Drive timing optimization and constraint development for complex mixed-signal systems

Execute analog circuit design tasks including simulation setup

testbench development

and schematic optimization using Cadence ADE

Perform comprehensive mixed-signal verification encompassing analog simulations

Analyze simulation results for power

and reliability compliance

Investigate and resolve complex issues in analog testbenches and mixed-signal simulations

Root-cause analysis of pre-silicon design challenges with systematic corrective action implementation

Develop behavioral models to improve simulation accuracy and efficiency

Advance verification flows and methodologies supporting evolving mixed-signal design requirements

Contribute to automation initiatives using scripting and emerging AI technologies

How You'll Work.

Team & Collaboration

Working in a collaborative environment with analog designers and system architects; Collaborate across disciplines with analog designers, digital architects, RTL teams, and physical design engineers; effective team collaboration capabilities

Communication Scope

Good communication skills

Full Job Description

# **Job Details:** ## Job Description: **_The Role and Impact_ ** Join Intel's cutting-edge mixed-signal IP development team as a Senior Mixed Signal Design Engineer. This role combines analog circuit design expertise with specialized focus on static timing analysis for next-generation mixed-signal systems. You'll drive timing closure across analog-digital interfaces while supporting comprehensive design verification activities that directly impact Intel's industry-leading products. Working in a collaborative environment with analog designers and system architects, you'll leverage tools like Cadence ADE to execute simulations, debug complex testbenches, and optimize circuit performance. This position offers significant opportunities to enhance verification methodologies and contribute to behavioral modeling initiatives that accelerate silicon success. If you are passionate about analog circuit design combined with mixed-signal verification (especially static timing analysis), and you thrive in a fast-paced, collaborative setting, we encourage you to apply. **Key Responsibilities:** **Static Timing Analysis & Design Closure** * Lead static timing analysis (STA) execution for mixed-signal designs, ensuring robust timing closure across analog-digital interfaces * Drive timing optimization and constraint development for complex mixed-signal systems **Analog Circuit Design & Verification** * Execute analog circuit design tasks including simulation setup, testbench development, and schematic optimization using Cadence ADE * Perform comprehensive mixed-signal verification encompassing analog simulations, behavioral modeling, and timing analysis * Analyze simulation results for power, performance, and reliability compliance **Debug & Problem Resolution** * Investigate and resolve complex issues in analog testbenches and mixed-signal simulations * Root-cause analysis of pre-silicon design challenges with systematic corrective action implementation * Collaborate across discip

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