Weekday AI

AnalogLayoutEngineer

₹8–10L Hyderabad, Telangana, India FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Senior candidates.

The Brief

“Analog Layout Engineer at Weekday AI. Skills: Analog Layout Design, Custom Layout Design, Cadence Virtuoso XL, Physical Verification. Develop custom layouts. Implement custom layouts”

What You'll Achieve.

Deliver robust silicon-ready designs

Industry & Context.

Problems you'll solve

Problem-solving capabilities; Analytical thinking

What They're Looking For.

Must Have

4+ years Analog Layout Engineering, Custom Layout Design experience, Cadence Virtuoso XL (VXL) expertise, Analog and mixed-signal design fundamentals, Physical verification flows knowledge, Matching techniques understanding, Parasitic management understanding, Electromigration understanding, Latch-up prevention understanding, Crosstalk mitigation understanding, IR-drop analysis understanding, Semiconductor process technologies familiarity, Design rules familiarity, Fabrication requirements familiarity

Nice to Have

Layout optimization experience

What You'll Do.

Develop custom layouts

Implement custom layouts

Meet design constraints

Meet process constraints

Create high-quality layouts

Design layouts for IPs

Design layouts for critical analog blocks

Design layouts for high-speed circuits

Perform floorplanning

Execute physical verification checks

Debug physical verification checks

Analyze layout-related issues

Resolve layout-related issues

Apply analog layout best practices

Address electromigration challenges

Address latch-up challenges

Address coupling challenges

Address crosstalk challenges

Address IR drop challenges

Address parasitic effects challenges

Optimize layouts for speed

Optimize layouts for capacitance

Optimize layouts for power consumption

Optimize layouts for signal integrity

Optimize layouts for area

Support Engineering Change Orders

Support Layout Change Orders

Support Design for Manufacturability

Ensure adherence to technology design rules

Ensure adherence to project guidelines

Ensure adherence to quality standards

Collaborate with design engineers

Understand circuit requirements

Implement optimal layout solutions

Participate in design reviews

Contribute to process improvements

How You'll Work.

Team & Collaboration

Cross-functional engineering teams; Circuit designers; Verification teams

Communication Scope

Verbal communication; Written communication

Full Job Description

**This role is for one of the Weekday's clients** **Salary range: Rs 800000 - Rs 1000000 (ie INR 8-10 LPA)** Experience: 4+ yrs Location: Hyderabad Job Type: full-time We are seeking a highly skilled Analog Layout Engineer with expertise in custom layout design for analog and mixed-signal integrated circuits. This role involves developing high-quality layouts for complex analog and high-speed circuit blocks while ensuring compliance with design specifications, process requirements, and physical verification standards. The ideal candidate will have strong hands-on experience with Cadence Virtuoso XL (VXL), a deep understanding of analog layout methodologies, and the ability to optimize layouts for performance, reliability, area, and manufacturability. You will collaborate closely with circuit designers and cross-functional engineering teams to deliver robust silicon-ready designs. **Requirements** ### Key Responsibilities * Develop and implement custom layouts for analog and mixed-signal circuit blocks while meeting design and process constraints. * Create high-quality layouts using Cadence Virtuoso XL (VXL) for complex analog and high-speed IPs. * Design layouts for critical analog blocks such as PLLs, ADCs, DACs, LDOs, Bandgap Reference Generators, Charge Pumps, Comparators, Oscillators, Current Mirrors, Differential Amplifiers, and Temperature Sensors. * Design layouts for high-speed circuits including transmitters, receivers, clock generation circuits, and related interfaces. * Perform floorplanning, placement, routing, and layout optimization to achieve performance, power, area, and reliability targets. * Execute and debug physical verification checks including LVS, DRC, and other layout validation activities. * Analyze and resolve layout-related issues impacting functionality, manufacturability, and performance. * Apply analog layout best practices including matching techniques, common-centroid layouts, shielding, guard rings, and symmetry considerations. * Add

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