MatX
AI
AIAcceleratorSiliconArchitect
Neural analysis suggests this role is
optimal for Mid+ candidates.
“AI Accelerator Silicon Architect at MatX. Skills: AI Accelerator Silicon Architect, AI compute subsystem architecture, ISA, connectivity, memories, control, architectural requirements from AI use cases, analytical and empirical performance analysis, microarchitecture fundamentals, latency, throughput, utilization, scalability, numeric formats, quantization, rounding, precision/performance tradeoffs, performance-optimization techniques in large-scale transformer models. Define the architecture fo”
What You'll Achieve.
delivering performant silicon architecture at the full-chip or subsystem level; help define the compute architecture for our next-generation GenAI accelerators
Industry & Context.
Conduct analytical and empirical performance analysis; Work through power, area, performance tradeoffs with stakeholders
This position requires access to information that is subject to U. S. export controls., This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U. S. export control laws without obtaining a license from U. S. export control authorities.
What They're Looking For.
Must Have
background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures, Experience translating workloads into hardware architecture, Solid microarchitecture fundamentals, First-principles understanding of latency, throughput, utilization, and scalability, Programming, code optimization, or kernel-level performance analysis experience, Excellent written and verbal communication skills, All candidates must be authorized to work in the United States, work from our offices in Mountain View Tuesdays-Thursdays, capacity to perform job functions in compliance with U. S. export control laws without obtaining a license from U. S. export control authorities
Nice to Have
Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs, Familiarity with performance-optimization techniques in large-scale transformer models is a plus
What You'll Do.
Define the architecture for MatX’s AI compute subsystem
Derive architectural requirements from AI use cases
Conduct analytical and empirical performance analysis
performance tradeoffs with stakeholders
Support test plan reviews
first-silicon bring-up
and post-silicon debug
How You'll Work.
Team & Collaboration
Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA; Work through power, area, performance tradeoffs with stakeholders
Communication Scope
Excellent written and verbal communication skills
Full Job Description
What MatX Is Building MatX designs hardware tailored for the world’s best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world’s largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators. What You'll Do Define the architecture for MatX’s AI compute subsystem, including ISA, connectivity, memories, and control.. Derive architectural requirements from AI use cases. Conduct analytical and empirical performance analysis. Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA. Work through power, area, performance tradeoffs with stakeholders. Support test plan reviews, first-silicon bring-up, and post-silicon debug. Who You Are Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures. Experience translating workloads into hardware architecture. Solid microarchitecture fundamentals. First-principles understanding of latency, throughput, utilization, and scalability. Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs. Programming, code optimization, or kernel-level performance analysis experience. Excellent written and verbal communication skills. Familiarity with performance-optimization techniques in large-scale transformer models is a plus. Work Location This is a hybrid role based in our Mountain View, CA office, with i
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