Micron Technology

Technology

2026.02_IPDev_Layout_1

$7500–11000k ~AI est. Hashimoto, Japan FULL TIME
Market Sentiment
HIGH DEMAND

Neural analysis suggests this role is
optimal for Mid+ candidates.

The Brief

“2026. 02_IPDev_Layout_1 at Micron Technology. Skills: Layout design, Circuit design, Memory design. Translate schematics into layout. Meet engineering and process criteria”

Industry & Context.

Technology
Problems you'll solve

Issue resolution

What They're Looking For.

Must Have

Meet all engineering and process criteria, Understand circuit design protocols, Understand fab processes, Understand mask generation techniques, Understand tapeout processes

Nice to Have

AI tools to enhance resume

What You'll Do.

Translate schematics into layout

Meet engineering and process criteria

Organize logistics and resource allocations

Prioritize logistics and resource allocations

Develop methodologies for issue resolution

Apply layout techniques for circuits

Design digital circuits

Design analog circuits

Contribute to new product development

Assist with design of circuits

Assist with layout of circuits

Assist with optimization of circuits

Perform parasitic modeling

Assist in design validation

Assist in reticle experiments

Assist in tape-out revisions

Oversee layout process

Manage layout process

Perform floor-planning

Perform verification processes

Contribute to cross group communication

Work towards standardization

Work towards group success

Ensure accurate manufacturability

Solicit guidance from Standards group

Solicit guidance from CAD group

Solicit guidance from modeling group

Solicit guidance from verification group

Improve design quality

Drive innovation into memory generations

How You'll Work.

Team & Collaboration

Design groups; Engineering groups; Marketing groups; Probe groups; Assembly groups; Test groups; Process Integration groups; Product Engineering groups; Standards groups; CAD groups; Modeling groups; Verification groups

Process & Methodology

Logistics management, Resource allocation

Full Job Description

**Our vision is to transform how the world uses information to enrich life for _all_. ** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM Engineering Group (DEG) Layout Designer at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures ## Responsibilities will include, but are not limited to: * Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits * Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions * Overseeing and managing the layout process including floor-planning, placement, and routing * Performing verification processes with modeling and simulation using industry standard simulators * Contributing to cross group communication to work towards standardization and group success * Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product * Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality * Driving innovation into the

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